This invention relates generally to a structure and method of manufacturing of active semiconductor devices and, in particular, relates to a structure and method of manufacturing of bipolar transistors formed along the plane of a semiconductor substrate surface and, further, to a combination planar bipolar/MIS semiconductor transistor.
A known method employed for the manufacture of bipolar transistor elements, hereafter referred to as a "planar type bipolar" transistors due to their formation along the plane of semiconductor substrate surface, comprising spatially formed collector and emitter regions formed of first conductive type impurity diffusions between which is a region of a second conductive type that functions as a base. Such a second conductive type region may be a diffusion region or substrate. These regions are all part of a substrate wherein the collector and emitter regions of the first conductivity type are formed on the surface of the substrate, which is of a second conductive type. FIG. 11 shows this structure wherein n-type diffusion regions 32 and 34, for example, are formed in p substrate 31. Diffusion region 32 functions as a collector domain, diffusion region 34 as an emitter emitter domain, and region 36 between the collector and the emitter functions as the transistor base region. FIG. 12 illustrates a conventional structure of semiconductor device wherein a MIS type transistor and a planar type bipolar transistor are formed in separate regions on the same semiconductor substrate. In FIG. 12, a MIS type transistor is formed relative to region M and a planar type bipolar transistor is formed relative to region L. The MIS type transistor comprises gate electrode 43 separated from substrate 41 by thin insulating film 44. Diffused source domain 45 and drain domain 46 are formed on adjacent sides of gate 43 utilizing an impurity of a conductivity type opposite to that of semiconductor substrate 41. The planar type bipolar transistor is isolated from MIS transistor M by insulating or LOCOS film 42, and comprises an impurity diffusion region 47 of a conductive type opposite to that of semiconductor substrate 41 and two spaced diffusion regions 48 and 49, respectively comprising the collector and emitter regions, having the same conductivity type as substrate 41 formed on the surface of semiconductor substrate 41 in impurity diffusion region 47. The region 50 between collector region 48 and emitter region 49 is the transistor base region.
The rate of current amplification of a bipolar transistor is affected by the width of transistor base region 50 so that it is necessary to make the width of transistor base region 50 smaller in order to increase the current amplification rate or "Hfe" of the bipolar transistor. However, with miniaturization of the size of the transistor, the nonuniformity of the transistor base width materially effects the transistor operating properties in that these properties become nonuniform. Relative to conventional methods of manufacturing these semiconductor devices, the base width of the planar type bipolar transistor is determined by the diffusion of the impurity that forms the first conductive type diffusion layer. In other words, the base width of a planar type bipolar transistor is difficult to miniaturize because there is a limit with respect to the resolving power of photolithographic process. Also, the method of expanding the first conductive type impurity diffusion layer by heat diffusion in order to increase Hfe and thereby raise transistor performance tends to be easily affected by disorders occurring during the transistor fabrication process. Thus, the miniaturization of planar type bipolar transistors that retain high performance characteristics cannot be formed with uniform electrical properties in a repeatable manner to provide for high yield bipolar devices.
Further, in order to change the base width of the planar type bipolar transistor, it is correspondingly necessary to make changes in the photomask used in forming the first impurity type diffusions as well as making substantial changes in process conditions to make the desired changes.
Also, in the case of semiconductor devices wherein MIS type transistors and planar type bipolar transistors are mounted on a common semiconductor substrate, an increase in the level of integration of these combination semiconductor devices is difficult because the different types of transistors are formed in spatially separate portions of the semiconductor substrate, as illustrated in FIG. 11.
Lastly, in planar type bipolar transistors of the prior art, the base width is determined by the introduction of impurities in an impurity diffusion layer of the first conductive type. As a result, the base width of a planar type bipolar is difficult to miniaturize due to the limit in the degree of resolution obtainable in lithographic techniques. Also, widening the impurity diffusion layer of the first conductive type by hot diffusion in order to increase Hfe as a simplified way to make a high performance transistor has the effect of bringing disorder to the semiconductor process. Thus, it is not possible to form miniaturized or smaller scale, high capacity planar type bipolar transistors with uniformity relative to the electrical properties of the formed elements.
It is an object of the present invention to resolve the foregoing described problems in offering a method of forming planar type bipolar transistors having uniform electrical properties.
It is another object of this invention to provide a method of manufacturing planar type bipolar transistors of comparatively smaller size to those presently available.
It is a further object of this invention to provide a method of manufacturing of planar type bipolar transistors having high Hfe.